Vhsic HDL: VHDL code for Johnson counter using D Flip Flop
Simple SR Latch Simulation in VHDL(with Xilinx) doesn't oscillate - Stack Overflow
verilog - D flip flop with asynchronous level triggered reset - Electrical Engineering Stack Exchange
VHDL code for D Flip Flop - FPGA4student.com
VHDL code for counters with testbench, VHDL code for up counter, VHDL code for down counter, VHDL code for up-down counter | Coding, Counter, Counter counter